1. Field of the Invention
The present invention relates to a circuit that eliminates transient simultaneous conduction current at the output of a dual-potential-interface-buffer circuit-generally described as a power-rail translator-operating independently of the sequencing of the respective high-potential power rails and without significant power losses in the system. More particularly, the present invention is directed to a circuit that completely turns off the pullup transistor of the buffer circuit before turning on the pulldown transistor so as to prevent simultaneous conduction through those two transistors. Even more particularly, the present invention acts to delay the turn-on of the pulldown transistor during the transition from logic-high to logic-low at the output of the translator.
2. Description of the Prior Art
As detailed in the related application of Yarbrough and Chapin, recent advances in integrated circuits--particularly in the field of small computer devices such as laptop and handheld computers--have led to the need for translator circuits used to make the transition from circuitry powered by a particular high-potential power rail to circuitry powered by a different high-potential power rail. These translators direct logic signals from transistors operating at one logic-level swing range, e.g., from 0 V to 5 V nominal, to transistors operating at a second logic-level swing range, e.g., from 0 V to 3.3 V--or vice versa. However such translators are not limited to operation in those ranges alone. It is well known that such translators are necessary in order to provide for complete turn-on or turn-off of circuit transistors when, for example, the logic-high signal coming into the control node of a particular transistor is lower by a volt or more than the potential of the high-potential rail powering that transistor. Failure to minimize the difference between the potential of that input signal to the control node and the high-potential rail will allow that transistor to remain on when it should be off. In such a case, there exists a continuous current path when none should exist, leading to increased power dissipation. This undesirable current path is described by various names, including leakage current, static current, and quiescent current. Of course, this failure to achieve complete turn-off generally occurs in MOS transistors and PMOS transistors in particular.
One example of a translator circuit that operates independent of the power-up sequencing of the different high-potential rails and without static current (I.sub.CCt) is described in the related application and is illustrated in FIG. 1. In that translator circuit 10, the two different high-potential rails, designated generally as V.sub.CCA and V.sub.CCB, power the input stage 11 and the output stage 12, respectively, of the translator circuit 10. The translator circuit 10 provides for isolation of the two high-potential rails by eliminating any direct pathway between them. This is achieved by coupling the source nodes and the control nodes of the PMOS transistors of the output stage of the translator to the same high-potential rail rather than coupling either the source node or the control node of one or more of the output stage PMOS transistors to one of the two high-potential rails while the other of those two nodes is tied to the other high-potential rail. Through this design the gate-to-source potential difference is minimized so that the PMOS transistors of the translator circuit 10 are on when they should be on and off when they should be off. Static leakage current is thus avoided.
In order to achieve complete power supply isolation, the input stage 11 of the translator circuit 10 has a standard inverting transistor pair PA1,NA1 coupled to the first high-potential rail V.sub.CCA and to the common low-potential rail GND. The output stage 12 is coupled to the second high-potential rail V.sub.CCB and to the common GND. A data input signal V.sub.IN is coupled to the input stage 11. The output stage 12 includes a pullup/pulldown stage formed of a complementary transistor pair PB3, NB3. The output stage 12 also includes a first control stage and a second control stage operating in complementary fashion to control the pullup/pulldown stage and to turn completely on and completely off all PMOS transistors of the output stage 12.
The first control stage includes a first PMOS control transistor PB1 and a first NMOS control transistor NB1, wherein the control node of the first NMOS transistor is coupled to the data input signal V.sub.IN, its source to GND, and its drain to node B tied to the control node of PB1. The source of PB1 is coupled directly to V.sub.CCB and its drain is tied to a node linked to the control node of the pullup transistor PB3. The second control stage includes a second PMOS control transistor PB2 and a second NMOS control transistor NB2, wherein the control node of NB2 is coupled to the data signal transmitted by the input stage 11 at node A, its source is coupled to GND, and its drain is coupled to node C tied to the control nodes of the pullup transistor PB3 and the second PMOS control transistor NB2. The source of PB2 is coupled directly to V.sub.CCB and its drain is tied to node B.
The related translator circuit 10 provides for the appropriate transition from the input stage 11 to the output stage 12 when the potentials of their respective high-potential rails are unequal. Further, this is accomplished without creation of static current. However, in the particular situation when the input data signal switches from logic-high to logic-low, or vice-versa, there exists a period of time within which both transistors of the pullup/pulldown stage, PB3 and NB3 are both on. With both transistors conducting simultaneously, a transient feedthrough switching current is evident in the translator circuit 10. As with the static current problem noted in earlier translators, the feedthrough switching current dissipates power in the system. While this switching current is, by its nature, transient, unlike the continuous static current, it nevertheless reduces the switching speed of the circuit and does dissipate power. Further, in devices with fast edges, this transient simultaneous conduction current can be significant enough to create noise problems in the circuit, given the speed with which load capacitances must be charged/discharged. This problem can be of particular concern in advanced MOS devices with voltage swings greater than those experienced by bipolar devices.
In the related translator circuit illustrated in FIG. 1 it can be seen that when the data signal at V.sub.IN switches from logic-low to logic-high, the data signal from the output V.sub.OUT will be switched from logic-high to logic-low. That is, pullup transistor PB3 is turned off and pulldown transistor NB3 is turned on. Under ideal conditions, PB3 would be turned off completely before NB3 is switched on. However, NB3 is coupled directly to V.sub.IN while PB3 is controlled through several devices that slow the signal from the output of the input stage 11. As a result, NB3 is on while PB3 is in the process of being switched off--thus producing the transient simultaneous conduction current. This transient simultaneous conduction therefore exists during this switching, regardless of the potentials of V.sub.CCA and V.sub.CCB. Of course, when V.sub.IN switches from logic-high to logic-low there also exists a period of time when both PB3 and NB4 are off. Of course, there is no transient simultaneous conduction current in that situation.
Therefore, what is needed is a device that will minimize, or prevent, transient simultaneous conduction at the output stage of a translator circuit. Further, what is needed is a device that will minimize or eliminate transient simultaneous conduction at the output stage of a translator circuit without effecting the ability of that translator to provide translation from circuitry powered by a high-potential rail at one potential to circuitry powered by a second high-potential rail at a different potential and without static current.